TCS: Chiplet Design Transforms Data Centre Chip Innovation

As demand for AI computing continues to rise, data centres face intense pressure to support higher performance, scalability and efficiency. In this context, chiplet-based architecture emerges as a key solution, challenging traditional system-on-chip (SoC) models that have long driven semiconductor development.

Tata Consultancy Services (TCS) is at the centre of this shift, bringing decades of semiconductor experience and strategic collaboration to redefine chip design. Prasad Patchigolla, Vice President and Chief Technology Officer of Technology, Software and Services at TCS, outlines how this shift impacts the data centre sector, especially as it adapts to new-generation AI workloads.

"My role is to define technology vision, co-create foundational technologies and solutions with industry partners, academia and open-source communities and orchestrate ecosystems to re-imagine the way people live, societies function and enterprises operate," he says.

"At TCS, we are partnering with our customers to pioneer a new era of AI innovation – right from silicon to software. 

"Our collaborative approach ensures that every solution is optimised for performance and scalability, empowering our clients to stay ahead in the competitive landscape."

Traditional chips hit limits as data centre needs grow

The semiconductor sector has followed Moore’s Law for decades, doubling the number of transistors on integrated circuits roughly every two years.

The pattern delivers performance gains for a time, but the move towards two-nanometre chips introduces technical and economic challenges.

Each generation of monolithic chips demands a higher investment in design and manufacturing and with billions of transistors on a single die, yields decline while costs rise.

In a data centre context, where hardware must be cost-efficient and scalable, this model creates bottlenecks. Data centre operators cannot continue to rely on costly monolithic architectures to power AI and generative AI workloads.

Chiplets present a practical alternative. Rather than building one large SoC, chiplets divide functionality into smaller modules. These modules, or chiplets, can be independently designed, validated and manufactured. They can then be integrated into a single package, reducing the die size and improving production yields.

For AI deployments in hyperscale data centres, there is better performance at a lower cost with the ability to adapt quickly to changing computational requirements.

Chiplets enable faster time to market and cost-efficient scale

TCS is addressing these challenges through its Chiplet-based System Engineering Services, designed to help semiconductor firms shift to modular design. The approach speeds up time to market while reducing design complexity and cost.

Prasad says: "By breaking down complex designs into smaller modules that can be designed, validated and reused independently, we significantly cut development time and expense, lowering risk compared to building monolithic chips from scratch."

The approach offers flexibility vital for data centre chip development. TCS helps clients connect validated chiplet modules using standardised interfaces, simplifying integration and testing.

Designs can also be customised by combining general-purpose and specialised chiplets, enabling unique configurations optimised for AI workloads such as large language model training or edge inference.

Thermal management remains a key issue, especially in 3D stacking used for advanced packaging. Here, TCS also supports clients by designing and verifying critical interconnects and cooling solutions to enable dense and high-performance systems.

"Using chiplets, we can also accelerate design cycles by leveraging validated modules and connecting them with standardised interfaces," says Prasad. "At TCS, we support our clients by designing and verifying these critical interconnects and advanced packages, including addressing challenges like heat dissipation in 3D stacking, enabling greater flexibility, scalability and cost-efficiency, which are vital for the rapid pace of the AI revolution."

TCS has already worked with a major North American semiconductor company to streamline chiplet integration into a unified package, demonstrating the viability of this approach in bringing AI chips to market faster.

Interconnect and packaging advances underpin data centre gains

As chiplets move closer to mainstream use, the role of interconnects becomes critical. In traditional monolithic chips, all elements reside on a single silicon die, allowing fast communication. Chiplet-based systems, however, must rely on high-speed interconnects between discrete components inside one package.

"Interconnect performance is absolutely crucial for chiplets, it's the backbone of this new architecture," says Prasad.

For AI applications, the interface between memory and processors is often the performance bottleneck. High-Bandwidth Memory (HBM), which places memory and compute within the same package, helps reduce this. HBM is particularly useful for data centre chips designed to run AI and machine learning workloads that require high throughput and low latency.

Industry standards like Universal Chiplet Interconnect Express (UCIe) support this development. UCIe provides a unified, high-bandwidth, low-latency communication standard for chiplet integration across different vendors.

"Key breakthroughs and industry standards like UCIe are critical, providing a standardised, high-bandwidth, low-latency interface for seamless chiplet integration regardless of the manufacturer," says Prasad.

In addition to UCIe and HBM, packaging techniques such as 2.5D and 3D stacking help increase component density, although they introduce cooling challenges that TCS helps clients resolve.

Looking to the future, Prasad believes that chiplets will support specialised chip development across a broad range of applications, including hyperscale data centres and intelligent edge devices.

"This will allow chipmakers to rapidly create custom solutions for incredibly diverse applications, from hyperscale data centres training the largest models to tiny edge devices like robots, autonomous vehicles, smart appliances or industrial machinery with embedded intelligence."

Adaptability is essential for scaling AI capabilities without the constraints of Moore’s Law. Chiplet-based design brings new architecture to semiconductor design, enabling hardware that evolves with AI demands across all sectors.

"The path forward is clear: sustaining the next wave of AI will require more than incremental scaling of existing systems," he explains. "It calls for rethinking semiconductor design at a fundamental level."