Microchip Unveils New Switch for Modern AI Data Centres

Microchip Technology expands its Switchtec line with the launch of Gen 6 PCIe switches, targeting hyperscale data centres, AI compute environments and high-performance computing (HPC) facilities.

Built on a 3 nanometre (nm) process and supporting up to 160 lanes, the new switches offer higher bandwidth, lower latency and a range of features designed for modern data centre architectures.

Designed for the next wave of AI and HPC

Data centres running AI workloads increasingly require fast, direct communication between CPUs, GPUs, AI accelerators and storage devices. 

Microchip’s Switchtec Gen 6 PCIe switches address this with full support for PCIe 6.0, which doubles the bandwidth of PCIe 5.0 to 64 giga transfers per second (GT/s) per lane.

The bandwidth expansion helps eliminate bottlenecks between compute components, which can otherwise lead to idle processing time and inefficient resource use.

Brian McCarson, Corporate Vice President of Microchip’s Data Centre Solutions Business Unit, says: “Rapid innovation in the AI era is prompting data centre architectures to move away from traditional designs and shift to a model where components are organised as a pool of shared resources.

“By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy efficient switch we've ever produced.”

The Gen 6 line includes up to 160 lanes and supports 20 ports across 10 stacks. Each port includes hot-plug and surprise-plug controllers, which simplify maintenance and upgrades in live systems. 

The configuration helps optimise rack-level interconnects for GPU clusters and storage arrays handling large volumes of training data and inference requests.

Enhancing efficiency and reducing latency

Switchtec Gen 6 brings a range of features that make data movement more reliable and efficient. These include Flow Control Unit (FLIT) mode and lightweight Forward Error Correction (FEC), which improve the integrity of transmitted data.

FLIT mode replaces the variable-size packets of earlier PCIe versions with fixed-size flow units, making error detection and correction more predictable.

Dynamic resource allocation and multicast support allow data to be distributed across multiple devices in a single domain. This makes the switches suitable for workloads such as model training and simulation, where multiple compute resources must process shared data in parallel.

Non-Transparent Bridging (NTB) enables the connection of multiple host systems while maintaining isolation, supporting use cases where redundancy and failover are critical. In addition, integrated diagnostics, error containment, and bifurcation options at x8 and x16 provide flexible configuration for various system designs.

The switches also include an integrated MIPS processor and broad I/O compatibility, allowing data centre operators to customise deployments based on specific workload requirements. Input and output reference clocks are handled by PCIe stacks, with each stack supporting four input clocks.

Tools for integration and diagnostics

Microchip supports the Switchtec Gen 6 family with a range of development tools. These include the ChipLink diagnostic suite, which enables configuration, debug and performance analysis through a graphical user interface. 

ChipLink connects via in-band PCIe or out-of-band signals such as UART, TWI and EJTAG, allowing flexible monitoring and troubleshooting during development and in live environments.

An evaluation kit, the PM61160-KIT, is also available for testing and integration. It supports multiple interfaces and is designed to help engineers model and simulate real-world data centre environments before full deployment.

With post-quantum safe cryptography compliant with the Commercial National Security Algorithm (CNSA) Suite 2.0, Switchtec Gen 6 also addresses the security needs of enterprise, government and cloud data centre operators. Features such as hardware root of trust and secure boot help safeguard system integrity across distributed deployments.

By delivering PCIe 6.0 speeds with dense port configurations and security built-in, Microchip positions Switchtec Gen 6 as a central component for data centres scaling AI and HPC infrastructure.